1. Field of the Invention
The present invention relates to a design apparatus for a configurable processor for a target application, a design method for the same, and a library optimization method for the same. It particularly relates to a technique for automating extending hardware and defining extension instructions in a configurable-processor design phase.
2. Description of the Related Art
To design system LSIs such as the SoC (system on chip) in which a re-configurable processor capable of being added application-specific instructions is embedded, designers must design a source program for an algorithm to be used in a to-be-developed application system using a high level language such as C language and then carry out a high-level system simulation verifying whether or not a desired performance has been attained. If those verification results have not satisfied that desired performance, bottlenecks are then searched and identified. And an additionally extension instruction (user-defined instruction) is then defined, a region needing to be replaced with that extension instruction and/or a region needing to be replaced with specific hardware is selected, the present source program is re-written, and the system simulation is then carried out again, verifying whether or not that desired performance has been attained.
As a means to facilitate such series of operations, an apparatus that establishes a verification environment and a development tool (see Japanese Patent Application Laid-open No. 2002-230065) and an apparatus that aids a performance evaluation operation in the initial phase of an operation for distinguishing hardware sections from software sections (see Japanese Patent Application Laid-open No. 2000-57188), for example, are disclosed.
However, since most of the conventional operations for defining extension instructions, making a specification for an instruction set and selecting a source program region to be replaced with an extension instruction and/or a region to be replaced with specific hardware based on the analysis results, or related operations are manually carried out on a trial and error basis, those operations take a long time and a lot of work.
Moreover, since there are many selectable, extension instruction definition methods and extending methods including usage of extension instructions and specific hardware, finding an optimal definition method and an extending method therefrom requires verification of each method, which takes a very long time and a lot of work.
Furthermore, there is a problem with the conventional verification method of carrying out system simulation and verifying whether or not a desired performance has been attained. Particularly, since conventional analysis of a program-based operation is made based on the execution count for each source program function and execution count for each instruction, comprehensive judgment cannot be made. This is because the analysis based on each function merely allows rough analysis of the operation while the analysis based on each instruction loses the relationship between adjacent instructions.
Furthermore, there are no tools for automatically generating an extension instruction set that is newly defined by a user, which may be useful to run a source program.
Yet furthermore, even though the source program may be optimized using a newly defined, extension instruction, libraries to be used to compile the source program cannot be optimized.